1. Introduction
This invention relates to methods for the manufacture of multilayer circuit boards and to the boards produced thereby, and more particularly, to methods for making multilayer boards by sequential formation of layers having signal layers separated from each other by layers containing conductive interconnections using permanent light sensitive coatings.
2. Description of the Prior Art.
Multilayer circuit fabrication is a means for providing multiple circuits in minimal volume. Multilayer boards typically comprise a stack of layers with signal lines (conductors) separated by a power and/or ground plane layer with the signal lines on one layer connected to the signal lines of another layer by plated holes known as "buried vias". The several layers are frequently bonded together with a pre-preg of a B-stage resin impregnated into a glass cloth fabric. Thus a complex multilayer stack can be illustrated as follows (absent the pre-preg layers):
______________________________________ Layer 1 Signal via Layer 2 Signal Layer 3 Power Layer 4 Ground Layer 5 Signal via Layer 6 Signal Layer 7 Power Layer 8 Ground Layer 9 Signal via Layer 10 Signal Layer 11 Power Layer 12 Ground Layer 13 Signal via Layer 14 Signal etc. ______________________________________
Current processes for fabricating multilayered boards are extensions of methods used for fabricating double-sided boards. The conventional method comprises fabrication of separate innerlayers composed of circuit patterns with numerous conductors. These innerlayers are formed in a manner analogous to the formation of single-sided or double-sided boards. A photosensitive material is coated over the copper surfaces of a copper clad innerlayer material, imaged, developed and etched to form a conductor pattern in the copper cladding protected by the photosensitive coating. After etching, the photosensitive coating is stripped from the copper leaving the circuit pattern on the surface of the base material. A multilayer stack is then formed by preparing a lay-up of innerlayers comprising signal layers, ground plane layers, power plane layers, etc., typically separated from each other by a pre-preg which is a layer consisting of glass cloth impregnated with partially cured material, typically a B-stage epoxy resin. The outer layers of the stack (those on the top and bottom of the stack) often comprise copper clad glass filled epoxy board material with the copper cladding comprising the exterior surfaces of the stack. The stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin.
Interconnects or through-holes, buried vias and blind hole interconnects are used to connect circuit layers within the multilayer board. The buried vias are plated through holes connecting two sides of an innerlayer. Blind vias typically pass through one surface of the stack and pass into and stop within the stack. Regardless of the form of interconnection, holes are generally drilled at appropriate locations through the stack. The holes are catalyzed by contact of the multilayer structure with a plating catalyst and the hole walls are metalized, typically with electroless copper overplated with electrolytic copper, to provide electrical contact between circuit innerlayers.
The uses, advantages and fabrication techniques for the manufacture of multilayer boards are described by Coombs, Printed Circuits Handbook, McGraw Hill Book Company, New York, 2nd edition, pp. 20-3 to 23-19, 1979, incorporated herein by reference.
Multilayer boards have become increasingly complex. For example, the boards used for main frame computers may have as many as 36 layers of circuitry, with the complete stack having a thickness of about 1/4 inch. These complex boards are currently designed with 4 mil wide signal lines and 12 mil diameter vias for interconnecting signal line layers. For increased densification of a board, it would be desirable to reduce signal lines to a width of 2 mils or less and vias to a diameter of 2 to 5 mils or less.
Because of the number of layers comprising the multilayer board, and the practical necessity of minimizing thickness of complex multilayer boards, current manufacturing methods utilize innerlayer materials comprising a glass reinforced resin of about 4 to 5 mils in thickness. Typically, these innerlayer materials are clad with copper on both surfaces. Since the lamination of a multilayer stack is at a temperature above 150.degree. C., the laminate shrinks upon cooling to ambient temperature, but only to the extent permitted by the copper cladding. In other words, the copper cladding restrains shrinkage. If the copper is etched to form a discontinuous pattern such as a pattern of signal lines, laminate shrinkage is no longer restrained by copper cladding. Consequently, further shrinkage occurs to the extent permitted by the glass reinforced resin. The coefficient of expansion differential between the copper and glass reinforced resin has an adverse effect on dimensional stability, especially on larger parts. Another substrate limitation having an adverse effect on dimensional stability is the flimsiness of the glass reinforced resin since the substrate is sensitive to stretching.
The above described dimensional stability problems are minimal, if not non-existent, when the copper clad innerlayer material is utilized as a power plane on one surface and a ground plane on the other surface. The reason is that the etched copper is in a continuous pattern which retains the innerlayer material and prevents further shrinkage. In addition, the remaining copper eliminates stretching problems.
The lamination procedure for the formation of a multilayer stack typically includes a lay-up of the following components prior to lamination using heat and pressure:
Signal innerlayer PA1 pre-preg PA1 power/ground plane innerlayer PA1 pre-preg PA1 signal innerlayer PA1 pre-preg PA1 etc.
Extreme care must be exercised to avoid shifting of innerlayers during lamination. Otherwise, the layers will not be aligned and electrical contact between layers will not be achieved. In addition, caution must be exercised to avoid damage to narrow etched signal lines, especially when signal lines and open channels are opposite each other on both surfaces of the innerlayer. At this point, where open channels are opposite each other, because of copper removal, the total thickness of the innerlayer is that of the dielectric substrate which may be as thin as from about 4 to 5 mils.
When the components of a multilayer stack are laid up, as indicated above, air is necessarily trapped in the spaces adjacent to signal lines because a partially cured, solid pre-preg is laid over the signal lines which does not fill and cannot flow into the recesses between signal lines. Care has to be taken during lamination to evacuate entrapped air. Residual air pockets can cause defects and/or subsequent problems during use of the multilayer board. Consequently, it is highly desirable to find a method of manufacturing multilayer boards that avoids the problem of air entrapment.
A semi-additive method for the manufacture of multilayer printed circuit boards is disclosed in U.S. Pat. No. 3,791,858 incorporated herein by reference. In the process of this patent, an insulative substrate is flash coated with a conductive material such as a thin layer of copper. The copper is coated with a photosensitive material in a thickness equivalent to the desired conductor line of the circuit and a pin which is used as an interconnect between circuit planes. The photosensitive material is exposed and developed and the flash coat of conductive material bared by development of the photosensitive coating is electroplated, typically with copper, whereby copper deposits over the conductive material filling the channels within the photosensitive material and creating the pin interconnects where desired. The photoresist is then removed, the underlying flash coating of conductive material etched and the photosensitive coating material is replaced with a dielectric material. The process may be repeated as many times as desired until a monolithic multilayer stack of circuits is created having pins interconnecting the circuit planes.
It is believed that the process of the above patent is not in commercial use because of inherent difficulties with the process. For example, using electroplating techniques to plate interconnects is believed to place a lower limit on the diameter of the holes or pins because of inadequate throwing power or other limitations. In addition, the process is cumbersome because the process sequence comprises excessive steps such as applying a flash coat, applying a photosensitive material, then removing and replacing this photosensitive material with a dielectric and etching to remove the flash coat. Finally, for the process to be operative, the interconnect must be filled with metal. This precludes the option of plating only the hole wall so that a device can be soldered into a hole interconnect.